View MT9M019_2170983.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by aptina without notice. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 1 ?2006 aptina imaging corporation all rights reserved. 1/5-inch 1.3mp cmos digital image sensor MT9M019 data sheet for the latest MT9M019 data sheet, refer to aptinas web site at www.aptina.com features ? digitalclarity ? cmos imaging technology ?low dark current ? simple two-wire serial interface ? auto black level calibration ? support for external led or xenon flash ? high frame rate preview mode with arbitrary down- size scaling from maximum resolution ? programmable controls: gain, frame size/rate, exposure, left?right and top?bottom image reversal, window size, and panning ?smia-compatible ? data interface: ccp2-compliant sub-low-voltage differential signalling (sub-lvds) ? on-chip phase-locked loop (pll) oscillator ? bayer pattern downsize scaler ? superior low-light performance applications ? cellular phones ? digital still cameras ?pc cameras ?pdas general description the aptina ? MT9M019 is a 1/5-inch sxga-format cmos active-pixel digital image sensor with a pixel array of 1280h x 1024v (1288h x 1032v including bor- der pixels). it incorporates sophisticated on-chip cam- era functions such as windowing, mirroring, column and row skip modes, and snapshot mode. it is pro- grammable through a simple two-wire serial interface and has very low power consumption. the MT9M019 digital image sensor features digital- clarity?aptina?s breakthrough low-noise cmos imag- ing technology that achieves near-ccd image quality (based on signal-to-noise ra tio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. when operated in its default mode, the sensor gener- ates a sxga image at 30 frames per second (fps). an on-chip analog-to-digital converter (adc) generates a 10-bit value for each pixel. ordering information table 2: available part numbers table 1: key performance parameters parameter value optical format 1/5-inch sxga (5:4) active imager size 2.83mm(h) x 2.27(v) 3.63mm diagonal (calculated from 1288 x 1032) active pixels 1288h x 1032v pixel size 2.2 x 2.2 m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 64 mp/s at 64 mhz system clock frame rate sxga (1280 x 1024) programmable up to 30 fps vga (640 x 480) programmable up to 60 fps adc resolution 10-bit, on-chip (61db) responsivity 1.14v/lux-sec dynamic range 67.27db snr max 36.4db supply voltage analog 2.4C3.1v (2.80v nominal) digital 1.7C1.9v (1.80v nominal) power consumption 190mw operating temperature C30c to +70c packaging die chief ray angle 24.77 at 85% image height part number description MT9M019d00stcc14bc1 bare die
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 2 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 ccp2 serial pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 slave address/data direction byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 message byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 single read from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 sequential read, start from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 sequential read, start from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 sequential write, start at random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 programming restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 output size restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 effect of scaler on legal range of output sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 effect of ccp2 class on legal range of ou tput sizes/frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 output data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 changing registers while streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 control of the signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 default power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 configuration of the pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 system states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power-on reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 soft reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 general purpose inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 streaming/standby control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 programming the pll divisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 influence of ccp_data_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 influence of ccp2_signalling_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 programming example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 image acquisition mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 3 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor table of contents pixel border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 horizontal mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 vertical flip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 frame rates at common image sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 valid data signal options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 integration time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 analog gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 using per-color or global gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 smia gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 aptina gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 gain code mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 sensor core digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 effect of data path processing on test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 solid color test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 100 percent color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 fade-to-gray color bars test pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 pn9 link integrity pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 test cursors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 pedestal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 extclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 operating voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 smia specification reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 4 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration: serial pixel data interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 4: single read from current locati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: single write to random location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: sequential write, start at random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: effect of limiter on smia data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: timing of smia data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: MT9M019 system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 12: MT9M019 smia profile 1, 2 clocki ng structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 13: MT9M019 smia profile 0 clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 14: pixel readout (no subsampling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 15: pixel readout (x_odd_inc = 3, y_o dd_inc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: pixel readout (x_odd_inc = 1, y_o dd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 17: pixel readout (x_odd_inc = 3, y_o dd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 18: xenon flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 19: led flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 20: led flash enabled following forc ed restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 21: 100 percent color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 22: fade-to-gray color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 23: test cursor behavior ? image_or ientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 24: die outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 25: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 26: cra vs. image height. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 27: internal power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 5 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: definitions for programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 5: programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: pll in system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 8: streaming/standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 9: valid divisor combinations (10 bits per pixel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 10: valid divisor combinations (8 bits per pixel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 11: default settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 12: row address sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 13: frame rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 14: test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 15: electrical characterist ics (extclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 16: two-wire serial register interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 17: electrical characteristics (serial pixel data interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 18: ac electrical characteri stics (control interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 19: power-on reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 20: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 21: smia characterization data table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 22: electrical characterist ics (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 23: absolute maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 6 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor functional overview functional overview the MT9M019 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 6 and 27 mhz. the maximum pixel rate is 64 mp/s, corresponding to a syst em clock rate of 64 mhz. a block diagram of the sensor is shown in figure 1. figure 1: block diagram the core of the sensor is a 1.3mp active-pix el array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chai n (providing offset correction and gain), and then through an adc. the output from the adc is a 10-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the pixel array contains optically active and light-shielded (?dark?) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (?black level? control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green/red pixels or blue/green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. the control registers, timing and control, and digital processing functions shown in figure 1 are partitioned into two logical parts: ? a sensor core that provides array control and data path corrections. the output of the sensor core is a serial ccp2 -compliant pixel data stream. ? additional functionality is required to support the smia standard. this includes a horizontal and vertical image scaler, a limite r, a data compressor, an output fifo, and a serializer. a flash output strobe is provided to allow an external xenon or led light source to synchronize with the sensor exposure time. active-pixel sensor (aps) array analog processing adc scaler limiter fifo timing control control registers data out two-wire serial interface sync signals
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 7 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor operating modes operating modes by default, the MT9M019 powers up as a sm ia-compatible sensor with the serial pixel data interface enabled. a typical configuration in this mode is shown in figure 2. figure 2: typical configuration: serial pixel data interface notes: 1. all power supplies should be adequately decoupled. 2. resistor value 1.5k is recommended, but may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on sclk at all times. 4. v aa and vaapix must be tied together. 5. the gpi pads can serve multiple features that can be reconfigured. the function will vary by application. v dd v dd ccp v aa vaapix 4 6C27 mhz 1.5k 2 1.5k 2, 3 s data sclk xshutdown (reset_n) test clk_p data_p data_n extclk d gnd a gnd digital ground analog ground digital power 1 analog power 1 to controller from controller flash clk_n v dd pll general purpose inputs (module id, s addr , standby) gpi[1:0] 5
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 8 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor signal descriptions signal descriptions table 3 provides signal descriptions for MT9M019 die. for pad location and aperture information, refer to the MT9M019 die data sheet. output data format ccp2 serial pixel data interface the MT9M019 serial pixel data interface impl ements data/clock and data/strobe signal- ling in accordance with the ccp2 specif ication. the raw8 and raw10 image data formats are supported. table 3: signal descriptions pad name pad type description extclk input master clock input. pll input clock. 6C27 mhz. reset_n (xshutdown) input asynchronous active low reset. when asserted , data output stops and all internal registers are restored to their factory default settings. sclk input serial clock for access to control and status registers. gpi[1:0] input general purpose inputs. after reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. any of these pads can be configured to provide hardware control of the standby and s addr functions. test input enable manufacturing test modes. wire to digital gnd for functional operation. s data i/o serial data for reads from and writes to control and status registers. data_p output differential ccp2 (sub-lvds) serial data (positive). data_n output differential ccp2 (sub-lvds) serial data (negative). clk_p output differential ccp2 (sub-lvds) serial clock/strobe (positive). clk_n output differential ccp2 (sub-lvds) serial clock/strobe (negative). flash output flash output. synchronization pulse for external light source. v aa 1, v aa 2, v aa 3, v aa 4 supply analog power supply. vaapix1, vaapix2 supply analog power supply for the pixel array. a gnd 1, a gnd 2, a gnd 3, a gnd 4 supply analog ground. v dd 1, v dd 2, v dd ccp supply digital power supply. d gnd 1, d gnd 2, d gnd 3 supply common ground for digital and i/o. v dd pll supply pll power supply.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 9 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the MT9M019. this interface is designed to be compatible with the smia 1.0 part2: ccp2 specification camera control interface (cci) which uses the electrical char- acteristics and transfer protocols of the i 2 c specification. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (sclk) that is an input to the sensor and us ed to synchronize transfers. data is trans- ferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd off-chip by a 1.5k resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the i 2 c specification enable the slave device to drive sclk low. however, the MT9M019 uses sclk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements, as follows: ? a (repeated) start condition ? a slave address/data direction byte ? an (a no) acknowledge bit ?a message byte ? a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while sclk an is high. at the end of a transfer, the master can generate a start condition without previ- ously generating a stop condition; this is known as a ?r epeated start? or ?restart? condi- tion. stop condition a stop condition is defined as a low-to-high transition on s data while sclk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the MT9M019 are 0x20 (write address) and 0x21 (read address)
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 10 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor two-wire serial register interface in accordance with the smia specification. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by asserting the s addr input signal through gpi inputs or register programmable. an alternate slave address can be programmed through r0x30fc?d. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the i 2 c specification and is defined as part of the smia cci. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when sclk is low and must be stable while sclk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is auto-incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no- acknowledge bit.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 11 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 3 on page 11) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no- acknowledge bit followed by a stop condition. figure 3 shows how the internal register address maintained by the MT9M019 is loaded and incremented as the sequence proceeds. figure 3: single read from random location single read from current location this sequence (figure 4) performs a read using the current value of the MT9M019 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 4: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+ 1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 12 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 5) starts in the same way as the single read from random loca- tion (figure 3). instead of generating a no-ackno wledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 5: sequential read, start from random location sequential read, start from current location this sequence (figure 6) starts in the same wa y as the single read from current location (figure 4 on page 11). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master gene rates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 6: sequential read, start from current location single write to random location this sequence (figure 7) begins with the mast er generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 7: single write to random location slave address 0 s sr a reg address[15:8] a read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+ 1 m+3 a a 1 a a read data read data m+l-2 m+l-1 m+l a s a read data read data previous reg address, n n+1 n+2 n+l-1 n+ l a read data slave address a a 1 read data a s s slave address 0 s a reg address[15:8] a reg address[7:0] a write data p previous reg address, n reg address, m m+ 1 a a
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. MT9M019 ds - rev. f 5/10 en 13 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 8) starts in the same way as the single write to random location (figure 7). instead of generating a no-acknowl edge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been writte n. the write is terminated by the master generating a st op condition. figure 8: sequential writ e, start at random location slave address 0 s a reg address[15:8] a write data write data a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a write data write data m+l-2 m+l-1 m+ l a a s
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 14 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions programming restrictions the smia specification imposes a number of programming restrictions. an implemen- tation naturally imposes additional restrictions. table 5 shows a list of programming rules that must be adhered to for correct operation of the MT9M019. it is recommended that these rules are encoded into the device driver stack, either implicitly or explicitly. table 4: definitions for programming rules name definition xskip if (x_odd_inc == 1) xskip = 1 else xskip = 2 yskip if (y_odd_inc == 1) yskip = 1 else yskip = 2 table 5: programming rules parameter minimum value maximum value origin coarse_integration_time coarse_integration_time_min frame_length_lines - coarse_integration_time_max_ margin smia fine_integration_time fine_integration_time_min line_length_pck - fine_integration_time_max_m argin smia digital_gain_* digital_gain_min digital_gain_max smia digital_gain_* is an integer multiple of digital_gain_step_size smia frame_length_lines min_frame_length_lines max_frame_length_lines smia line_length_pck min_line_length_pck max_line_length_pck smia line_length_pck ((x_addr_end - x_addr_start + 1)/ xskip) + min_line_blanking_pck smia frame_length_lines ((y_addr_end - y_addr_start + 1)/ yskip) + min_frame_blanking_lines smia x_addr_start x_addr_min x_addr_max smia x_addr_end x_addr_start x_addr_max smia (x_addr_end - x_addr_start+ 1) must be positive must be positive smia x_addr_start[0] 0 0 smia x_addr_end[0] 1 1 smia y_addr_start y_addr_min y_addr_max smia y_addr_end y_addr_start y_addr_max smia (y_addr_end - y_addr_start + 1) must be positive must be positive smia y_addr_start[0] 0 0 smia y_addr_end[0] 1 1 smia x_even_inc min_even_inc max_even_inc smia x_even_inc[0] 1 1 smia y_even_inc min_even_inc max_even_inc smia y_even_inc[0] 1 1 smia x_odd_inc min_odd_inc max_odd_inc smia x_odd_inc[0] 1 1 smia y_odd_inc min_odd_inc max_odd_inc smia y_odd_inc[0] 1 1 smia scale_m scaler_m_min scaler_m_max smia
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 15 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions notes: 1. smia fs = smia functional specifications. scale_n scaler_n_min scaler_n_max smia x_output_size 256 (this is enforced in hardware: values lower than this are treated as 256) 1288 minimum from smia fs 1 section 5.2.2.5 maximum is a consequence of the output fifo size on this implementation. x_output_size[0] 0 (this is enforced in hardware: bit[0] is read-only) 0 smia fs section 5.2.2.2 y_output_size 2 frame_length_lines minimum ensures 1 bayer row-pair. maximum avoids output frame being longer than pixel array frame. y_output_size[0] 0 (this is enforced in hardware: bit[0] is read-only) 0 smia fs section 5.2.2.2 with subsampling, start and end pixels must be addressed (impact on x/y start/end addresses, function of image orientation bits) smia fs errata subsampling on page 29. table 5: programming rules (continued) parameter minimum value maximum value origin
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 16 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions output size restrictions the ccp2 specification imposes the restriction th at an output line shall be a multiple of 32 bits in length. this imposes an additi onal restriction on the legal values of x_output_size: ? when ccp_data_format[7:0] = 8 (raw8 data), x_output_size must be a multiple of 4 (x_output_size[1:0] = 0). ? when ccp_data_format[7:0] = 10 (raw10 data), x_output_size must be a multiple of 16 (x_output_size[3:0] = 0). this restriction can be met by rounding up x_output_size to an appropriate multiple. any extra pixels in the output image as a result of this rounding contain undefined pixel data but are guaranteed not to cause false synchronization on the ccp2 data stream. there is an additional restriction that x_outp ut_size must be small enough such that the output row time (set by x_output_size, the framing and crc overhead of 12 bytes, the ccp_signalling_mode, and the ou tput clock rate) must be less than the row time of the video array (set by line_length_pck and the video timing clock rate). effect of scaler on legal range of output sizes when the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size gene rated by the scaler. the MT9M019 will not operate properly if the x_output_size and y_ou tput_size are significantly larger than the output image. to understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). this situation is shown in figure 9. figure 9: effect of limiter on smia data path in figure 9, three different stages in the smia data path are shown. the first stage is the output of the sensor core. the core is running at full resolution and x_output_size is set to match the active array size. the line_val id signal is assert ed once per row and remains asserted for n pixel times. the pixel_valid signal toggles with the same timing as line_valid, indicating that all pixels in the row are valid. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line valid s caler output: scaled to half size line valid pixel valid l imiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 line valid pixel valid pixel valid
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 17 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions the second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. the effe ct of the scaler is to combine groups of pixels. therefore, the row time remains the same but only half the pixels out of the scaler are valid. this is signalled by transitions in pixel_valid. overall, pixel_valid is asserted for ( n /2) pixel times per row. the third stage is the output of the limiter when the x_output_size is still set to match the active array size. because the scaler has reduced the amount of valid pixel data without reducing the row time, the limiter attempts to pad the row with ( n /2) additional pixels. if this has the effect of extending line_valid across the whole of the horizontal blanking time, as shown figure 9 on page 16, the mt9m 019 will cease to generate output frames. a correct configuration is shown in figure 10. this figure shows the x_output_size reduced to match the output size of the scaler . in this configuration, the output of the limiter does not extend line_valid. figure 9 on page 16 also shows the effect of the output fifo, which forms the final stage in the smia data path. the output fifo merges the intermittent pixel data back into a contiguous stream. although not shown in this example, the output fifo is also capable of operating with an output clock that is at a different frequency from its input clock. figure 10: timing of smia data path effect of ccp2 class on legal range of output sizes/frame rate the pixel array readout rate is set by line_length_pck * frame_length_lines . with the default register values one frame time takes 1,854 * 1,109 = 2,056,086 pixel periods. this value includes vertical and horizontal blan king times, so that the full-size image 1280 x 1026 (1,024 lines of pixel data, 2 lines of embedded information) forms a subset of these pixels. when the internal clock is running at 64 mhz, this frame time corresponds to 2,056,086/ 64e6 = 32.1263 milliseconds, giving rise to a frame rate of 31.13 fps. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line valid s caler output: scaled to half size line valid pixel valid l imiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 pixel valid line valid pixel valid o utput fifo: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 line valid pixel valid
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 18 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions each pixel is 10 bits, by default. this data rate requires the serial interface to transmit 2,056,086 * 10 bits in 32.1263 milliseconds. that is, the serial data rate must be 10x the pixel rate?640 mb/s. the ccp2 specification shows that class 0 (data/ clock) runs up to 208 mb/s. therefore, it is not possible to transmit full-resolution images at 31 fps using ccp2 class 0. changing the ccp_data_format (to use 8 bits per pixel) reduces the bandwidth requirement, but is not enough to allow full-resolution operation. the only way to get a full image out is to redu ce the pixel clock rate until it is appropriate for the maximum ccp2 class 0 data rate. this requires the pixel rate to be reduced to 20.8 mhz. this has the side effect of reducing the frame rate. repeating the calculation above, at 20.8 mhz internal clock, this corresponds to 2,056,086/20.8e6 = 98.85msec, giving rise to a frame rate of 10.12 fps. note: the output pixel rate cannot be greater than 20.8 mhz in ccp class 0 mode, but the internal pixel rate (vt domain) which controls the frame rate can be modified to run faster by changing the horizontal blanking. to use ccp2 class 0 with an internal cloc k of 64 mhz it is necessary to reduce the amount of output data. this can be achieved by changing x_output_size, y_output_size so that less data comes out per frame. a change to the output size can be done in conjunction with windowing the image from the sensor (by adjusting x_addr_start, x_addr_end, y_addr_start, y_addr_end ) or by enabling the scaler. output data timing the output fifo acts as a boundary between two clock domains. data is written to the fifo in the vt (video timing) clock domain. data is read out of the fifo in the op (output) clock domain. when the scaler is disabled, the data rate in the vt clock domain is constant and uniform during the active period of each pi xel array row readout. when the scaler is enabled, the data rate in the vt clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. a key constraint when configuring the clock fo r the output fifo is that the frame rate out of the fifo must exactly match the frame rate into the fifo. when the scaler is disabled, this constraint can be met by imposi ng the rule that the row time on the ccp2 data stream must be greater than or equal to the row time at the pixel array. the row time on the ccp2 data stream is calculated fr om the x_output_size and the ccp_data_format (8 or 10 bits per pixel), and must include the time taken in the ccp2 data stream for start of frame/row, end of row/ frame and checksum symbols. caution if this constraint is not met, the fifo will either underrun or overrun. fifo underrun or overrun is a fatal error condition that is signalled thro ugh the data path_status register (r0x306eCf).
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 19 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor programming restrictions changing registers while streaming the following registers should only be repr ogrammed while the sensor is in software standby: ? ccp2_channel_identifier ? ccp2_signalling_mode ? ccp_data_format ?scale_m ?vt_pix_clk_div ? vt_sys_clk_div ? pre_pll_clk_div ? pll_multiplier ? op_pix_clk_div ?op_sys_clk_div ? profile 0/1, 2 selection
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 20 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor control of the signal interface control of the signal interface this section describes the operation of the signal interface in all functional modes. serial register interface the serial register interface uses the following signals: ?sclk ?s data ?s addr sclk is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place th is signal in high-z, an external pull-up resistor should be connected to this signal. s data is a bidirectional signal. an external pull-up resistor should be connected on this signal. s addr in an input-only signal and must always be driven to a valid logic level for correct operation. in most applications this input will be hardwired to logic ?0? if a gpi is used. there is no dedicated s addr pin. this interface is described in detail in ?two-wire serial register interface? on page 9. default power-up state at power-up and after a hard or soft reset, the reset state of the MT9M019 is under smia operation and the ccp2 high -speed serial interface. serial pixel data interface the serial pixel data interface uses the following output-only signal pairs: ?datap ?datan ?clkp ?clkn the signal pairs are driven differentially using sub-lvds switching levels. this interface conforms to the smia 1.0 ccp2 requirements and supports both data/clock signalling and data/strobe signalling. the datap, datan, clkp, and clkn pads are turned off if the smia serial disable bit is asserted (r0x301a?b[12] = 1) or when th e sensor is in the soft standby state. in data/clock mode, the clock remains high wh en no data is being transmitted. in data/ strobe mode before frame start, clock is low and data is high. configuration of the pixel data interface fields in r0x301a?b are used to configure the operation of the pixel data interface.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 21 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor control of the signal interface system states the system states of the MT9M019 are repres ented as a state diagram in figure 11 and described in subsequent sections. the effect of reset_n on the system state and the configuration of the pll in the different states are shown in table 6. the sensor?s operation is broken down into three separate states: hardware standby, software standby, and streaming. the tran sition between these states might take a certain amount of clock cycles, as outlined in table 6. figure 11: MT9M019 system states table 6: pll in system states state extclks pll powered off vco powered down pll lock 6750 vco powering up and locking, streaming vco running, pll output active wait for frame end powered off por active hardware standby internal init ( 800 extclks ) software standby streaming wait for frame end pll lock (6750 extclks ) software reset powered on por completed hardware reset released init finished p or not yet completed hardware reset active init not completed pll aquiring lock mode_select =1 lock acquired mode_select =0 frame in progre ss reset transition 1->0 (asynchronous from every state) power supply turned off . (asynchronous from every state)
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 22 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor control of the signal interface power-on reset sequence when power is applied to the MT9M019, it enters a low-power hardware standby state. exit from this state is controlled by the later of two events: 1. the negation of the reset_n input. 2. a timeout of the internal power-on reset circuit. it is possible to hold reset_n permanentl y negated and rely upon the internal power- on reset circuit. the reset_n signal is functionally equivalent to the smia-specified xshutdown signal. when reset_n is asserted it asynchronously resets the sensor, truncating any frame that is in progress. while reset_n is asserted (or the internal power-on reset circuit is active) the MT9M019 is in its lowest-powered, powered-up state; the internal pll is disabled, the ccp2 serializer is disabled an d internal clocks are gated off. when the sensor leaves the hardware standby st ate, it performs an internal initialization sequence that takes 800 extclk cycles. af ter this, it enters a low-power software standby state. while the initialization sequ ence is in progress, the MT9M019 will not respond to read transactions on its two-wire serial interface. therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, r0x0000. while the initialization sequ ence is in progress, the sensor will not respond to its device address and so reads from the sensor will result in a nack on the two-wire serial interface bus. when the sequ ence has completed, reads will return the operational value for the register (0x14 if r0x0000 is read). when the sensor leaves software standby mo de and enables the vco, an internal delay will keep the pll disconnected for 6,750 extclks so that the pll can lock. soft reset sequence the MT9M019 can be reset under software co ntrol by writing ?1? to software_reset (r0x0103). a software reset asynchronously re sets the sensor, truncating any frame that is in progress. the sensor briefly enters th e hardware standby state and then starts its internal initialization sequence. at this point, the behavior is exactly the same as for the power-on reset sequence. signal state during reset table 7 on page 23 shows the state of the signal interface during hardware standby (reset_n asserted) and the default state during software standby (after exit from hard- ware standby and before any registers within the sensor have been changed from their default power-up values).
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 23 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor control of the signal interface general purpose inputs the MT9M019 provides two general purpose inputs. after reset, the input pads associ- ated with these signals are powered down by de fault, allowing the pads to be left discon- nected/floating. the general purpose inputs are enabled by setting reset_register[8] (r0x301a?b). once enabled, both inputs must be driven to valid logic levels by external signals. the state of the general purpose inputs can be read through gpi_status[1:0] (r0x3026?7). in addition, each of the following functions ca n be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input: ?output enable other uses: ?s addr pin (choose i 2 c device address: r0x31fc?d[7:0] or r0x31fc?d[15:8]) ? module id (the state of the two pins can be read back if different module versions tie the pins differently) ? trigger (see the sections below) ? standby functions (see the following sections) the gpi_status register is used to associ ate a function with a general purpose input. streaming/standby control the MT9M019 can be switched between its so ft standby and stream ing states under pin or register control, as shown in table 8. se lection of a pin to use for the standby func- tion is described in ?general purpose inputs? on page 23. the state diagram for transi- tions between soft standby and streaming states is shown in figure 11 on page 21. table 7: signal state during reset pad name pad type hardware standby software standby extclk input enabled. must be driven to a valid logic level. reset_n (xshutdown) input enabled. must be driven to a valid logic level. scl input enabled. must be pulled up or driven to a valid logic level. sda i/o enabled as an input. must be pulled up or driven to a valid logic level. flash output high-z. logic 0. datap output high-z. datan output clkp output clkn output gpi(1:0) input powered down. can be left disconnected/floating. test input enabled. must be driven to a logic 0. table 8: streaming/standby standby streaming r0x301a ? b[2] description disabled 0 soft standby disabled 1 streaming x0 soft standby 01 streaming 1x soft standby
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 24 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor clocking clocking the MT9M019 contains a phase-locked loop (pll) for timing generation and control. the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks. both smia profile 0 clock scheme and prof ile 1, 2 are supported. the clocking scheme can be selected by either setting register 0x306e?f[7] to 0 for profile 0 or to 1 for profile 1, 2. figure 12: MT9M019 smia profile 1, 2 clocking structure figure 12 shows the different clocks and (in courier font) the names of the registers that contain or are used to control their va lues. the figure shows the default setting for each divider/multipler control register and the range of legal values for each divider/ multiplier control register. the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock ? the divisors that are used to control each clock the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met. ? the minimum/maximum value for the divider/multiplier must be met. ? the value of pll_multiplier should be a multiple of 2. ? the op_pix_clk must never run faster than the vt_pix_clk to ensure that the ccp2 output data stream is contiguous. ? given the maximum programmed line length, the minimum blanking time, the maximum image width, the available pll di visor/multiplier values, and the require- ment that the output line ti me (including the necessary bl anking) must be output in a pre pll divider vt _sys_clk divider pll multiplier vt _ pix_clk divider op_sys _clk divider op_pix_clk divider op_pix_clk extclk external input clock pll input clock pll output clock video timing system clock op_ pix _clk _ div 10( 8, 10) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz vt_sys_clk_div 2 (2) vt_pix_clk op_sys_clk_div 1 (1, 2, 3.....32) vt_sys_clk_freq_mhz op_sys_clk pll_multiplier 80 (1, 2, 3.....254) pre_pll_clk_div 2 (1, 2, 3.....32) ext_clk_freq_mhz vt_pic_clk_div 5 (4, 5, 6......10)
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 25 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor clocking time equal to or less than the time defined by line_length_pck, the valid combinations of the clock divisors are as shown in table 9 and table 10. pll input clock frequency range is 2.0 ?11.5 mhz. the usage of the output clocks is shown below: ? vt_pix_clk is used by the sensor core to control the timing of the pixel array. the sensor core produces one 10-bit pixel each vt_pix_clk period. the line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the vt_pix_clk period. ? op_pix_clk is used to load parallel pixel data from the output fifo to the ccp2 serial- izer. the output fifo generates one pixel ea ch op_pix_clk period. the pixel is either 8-bit or 10-bit depending upon the output data format, controlled by the ccp_data_format register (r0x0112?3). ? op_sys_clk is used to generate the serial data stream on the ccp2 output. the rela- tionship between this clock frequency an d the op_pix_clk frequency is dependent upon the output data format. in profile 1,2, the output clock fr equencies can be calculated as: (eq 1) (eq 2) table 9: valid divisor combinations (10 bits per pixel) op_sys_clk_div vt_pix_clk_div 14, 5 2, 4, 6, 8 4, 5, 6, 7, 8, 9, 10 10 5, 6, 7, 8, 9, 10 12 6, 7, 8, 9, 10 14 7, 8, 9, 10 16 8, 9, 10 18, 20 9, 10 22 10 table 10: valid divisor combinations (8 bits per pixel) op_sys_clk_div vt_pix_clk_div 14 2 4, 5, 6, 7 8 4, 6, 8, 10 4, 5, 6, 7, 8, 9, 10 12 5, 6, 7, 8 9, 10 14, 16 6, 7, 8, 9, 10 18 7, 8, 9, 10 20 8, 9, 10 22, 24 9, 10 26 10 vt_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys_ clk_div*vt_pix_clk_div --------------------- --------------------- ---------------------- --------------------- ------------------ ------------- op_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys_clk_div*op_pix_clk_div -------------------- --------------------- --------------------- ---------------------- ----------------- ----------------- -
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 26 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor clocking (eq 3) figure 13: MT9M019 smia profile 0 clocking structure figure 13 shows the different clocks and (in courier font) the names of the registers that contain or are used to control their va lues. figure 13 shows the default setting for each divider/multipler control register and the range of legal values for each divider/ multiplier control register. the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock. ? the divisors that are used to control each clock. the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met. ? the minimum/maximum value for the divider/multiplier must be met. ? given the maximum programmed line length, the minimum blanking time, the maximum image width, the available pll di visor/multiplier values, and the require- ment that the output line ti me (including the necessary bl anking) must be output in a time equal to or less than the time defined by line_length_pck. pll input clock frequency range is 2.0 ?11.5 mhz. the usage of the output clocks is shown below: ? vt_pix_clk is used by the sensor core to control the timing of the pixel array. the sensor core produces one 10-bit pixel each vt_pix_clk period. the line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the vt_pix_clk period. ? vt_sys_clk is also used to generate the serial data stream on the ccp2 output. op_sys_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys_clk_div ------------------- ---------------------- --------------------- ------------------ - pre pll divider vt_sys_ clk divider pll multiplier vt_pix_clk divider extclk external input clock pll input clock pll output clock video timing system clock vt_sys_clk_div (1,2,3,4,6,8....) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier 80 (1,2,3....254) pre_pll_clk_div (1,2,4) vt_pix_clk vt_pix_clk_div 10 (10) op_sys_clk
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 27 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor clocking in profile 0 the output clock frequencies can be calculated as: (eq 4) (eq 5) (eq 6) programming the pll divisors the pll divisors should be programmed whil e the MT9M019 is in the software standby state. after programming the divisors, it is ne cessary to wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. an external timer will delay entering streaming mode by 6,750 extclks so that the pll can lock. the effect of programming th e pll divisors while the mt9m 019 is in the streaming state is undefined. influence of ccp_data_format the ccp_data_format register (r0x0112?3) cont rols whether the pixel data interface will generate 10 bits per pixel or 8 bits per pixel. the raw output of the sensor core is 10-bits per-pixel; the two 8-bit modes represent a co mpressed data mode and a mode in which the two least significant bits of the 10-bit data are discarded. when the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be programmed with the value 8. when the pixel data interface is generating 10 bits per- pixel, op_pix_clk_div must be programmed with the value 10. influence of ccp2_signalling_mode the ccp2_signalling_mode register (r0x0111) controls whether the serial pixel data interface uses data/strobe signalling or data/clock signalling. when data/clock signalling is selected, the pll_multiplier supports both odd and even values. when data/strobe signalling is selected, th e pll_multiplier only supports even values; the least significant bit of the programmed value is ignored and treated as ?0.? this behavior is a result of the implementati on of the ccp2 serializer and the pll. when the serializer is using data/strobe signalling , it uses both edges of the op_sys_clk and therefore that clock runs at one half of the bi t rate. all of the programmed divisors are set up to make this behavior invisible. for example, when the divisors are programmed to generate a pll output of 640 mhz, the actual pll output is 320 mhz but both edges are used. when the serializer is using data/clock signalli ng, it uses a single edge on the op_sys_clk and therefore that clock runs at the bit rate. to disguise this behavior from the programmer, the actual pll multiplier is right-shifted by 1 bit relative to the programmed value when ccp2_signalling_mode selects data/ strobe signalling. vt_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys_clk_div*10 --------------- ------------------ ----------------- ------------------ ----------------- - op_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys_clk_div*10 ---------------- ------------------ ------------------ ----------------- ---------------- - op_sys_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys_clk_div -------------------- --------------------- --------------------- ------------------ -
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 28 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor clocking programming example this section provides one programming example which is the default settings. for this example, a table of register values is shown (for example, table 11, default settings). the settings for the clock divisors show the "programmed value" and "apparent frequency." these values are consistent with MT9M019 smia profile 0 clocking structure and the associated equations for the different clocks. the table also shows the "effective value" and "actual frequency." these values are implementation details that reflect the internal operation of the clocks; they are cons istent with the descriptions given in ?influ- ence of ccp_data_format? on page 27. example: ? 10 bits per-pixel data ? ccp2 class 1/cl ass 2 signalling ? highest possible frame ra te at maximum resolution to meet the requirement for the highest possible frame rate, vt_pix_clk should run at 64 mhz. for 10 bits per-pixel operation, op_s ys_clk must run at 10x op_pix_clk. there- fore, op_sys_clk_div is set to 1 and op_pix_clk _div to 10, giving an overall divide-by-10 in the op clock domain. since vt_sys_clk_div is fixed at 2, the same divide-by-10 is achieved in the vt clock domain by setting vt_pix_clk_div to 5. as a result, the pll output frequency must be set to 64 * 10 = 640 mhz. there are various ways doing this, depending upon the fr equency of extclk. the register settings for this example and the resulting clock frequencies are shown in table 11. if the MT9M019 is programmed with these values (and all other registers are left at their default values), and is then pu t into streaming mode (mode_select=1) it will stream frames at full resolution (1,280 x 1,024 pixels) through its ccp2 interface at 31.1 fps. clock control the MT9M019 uses an aggressive clock-gating methodology to reduce power consump- tion. the clocked logic is divided into a number of separate domains, each of which is only clocked when required. when the MT9M019 enters a low-power state, almost all of the internal clocks are stopped. the only exception is that a small am ount of logic is clocked so that two-wire serial interface continues to respond to read and write requests. table 11: default settings register programmed value effective value clock apparent frequency actual frequency ccp_data_format 0x0a0a 10 bits per pixel C C C ccp2_signalling_mode 1 data/strobe signalling C -C C CCCextclk16mhz16mhz pre_pll_clk_div 2 2 pll_ip_clk 8 mhz 8 mhz pll_multiplier 80 40 pll_op_clk 640 mhz 320 mhz vt_sys_clk_div 2 1 vt_sys_clk 320 mhz 320 mhz vt_pix_clk_div 5 5 vt_pix_clk 64 mhz 64 mhz op_sys_clk_div 1 1 op_sys_clk 640 mhz 320 mhz op_pix_clk_div 10 5 op_pix_clk 64 mhz 64 mhz
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 29 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features features image acquisition mode the MT9M019 supports electronic rolling sh utter (ers) mode. when the MT9M019 is streaming, it generates frames at a fixed rate, and each fr ame is integrated (exposed) using the ers. when the ers is in use, ti ming and control logic within the sensor sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is fixed, le ading to a uniform integration time across the frame. when the integration time is chan ged (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of outp ut frames from the MT9M019 switches cleanly from the old inte gration time to the new while only gener- ating frames with uniform integration. window control the sequencing of the pixel array is cont rolled by the x_addr_start, y_addr_start, x_addr_end, y_addr_end registers. when the smia data path is enabled, the output image size is controlled by the x_ou tput_size and y_output_size registers. pixel border the default settings of the sensor provide a 1280h x 1024v image. a border of up to 4 pixels on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers and then adjusting the x_output_size and y_output_size registers accordingly. readout modes horizontal mirror when the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. changing horizontal_mirror caus es the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register (see r0x3024). vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. changing vertical_flip causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register (see r0x3024). subsampling the MT9M019 supports subsampling. subsampling reduces the amount of data processed by the analog signal chain in the sensor and thereby allows the frame rate to be increased. subsampling is enabled by setting x_odd_inc = 3 and/or y_odd_inc = 3.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 30 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features this will skip two rows/columns during read out and is equivalent to the skip2 readout mode provided by earlier aptina sensors. the effect of the different subsampling settings on the pixel array readout is shown in figures 14 through 17. figure 14: pixel readout (no subsampling) figure 15: pixel readout (x_odd_inc = 3, y_odd_inc = 1) x incrementing y incrementing x incrementing y incrementing
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 31 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features figure 16: pixel readout (x_odd_inc = 1, y_odd_inc = 3) figure 17: pixel readout (x_odd_inc = 3, y_odd_inc = 3) programming restrictions when subsampling when subsampling is enabled as a viewfinder mode, and the sensor is switched back and forth between full resolution and subsampling, it is recommended that line_length_pck be kept consta nt between the two modes. this allows the same integra- tion times to be used in each mode. when subsampling is enabled, it may be necessary to adjust the x_addr_end and y_addr_end settings. the values for these registers are required to correspond with rows/ columns that form part of the subsampling sequence. the adjustment should be made in accordance with the following rule: remainder = (addr_end - addr_start + 1) and 0x0002; if (remainder == 0) ad dr_end = addr_end - 2; x incrementing y incrementing x incrementing y incrementing
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 32 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features table 12 shows the row address sequencing fo r normal and subsampled (with y_odd_inc = 3) readout. the same sequencing applies to column addresses for subsampled readout. there are two possible subsampling sequences (because the subsampling sequence only read half of the rows and co lumns) depending upon the alignment of the start address. frame rate control the formula for calculating the frame rate of the MT9M019 is shown below: (eq 7) (eq 8) (eq 9) table 12: row address sequencing normal subsampled subsampled 00C 11C 2C2 3C3 44C 55C 6C6 7C7 line_length_pck x_addr_end - x_addr_start 1 + subsampling factor -------------------- ------------------ ----------------- ------------------ - min_line_blanking_pck + ?? ?? = frame_length_lines y_addr_end - y_addr_start 1 + subsampling factor ------------------- --------------------- ------------------ --------------- - min_frame_blanking_lines + ?? ?? = frame rate [fps] vt_pixel_clock_mhz * 1 6 10 () line_length_pck* frame_length_lines () --------------------- --------------------- --------------------- ------------------ -------------- =
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 33 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features frame rates at common image sizes table 13 shows the maximum frame rates that can be achieved at various common image sizes with a data rate limit of 640 mb/s (ccp2). the frame rates are shown with subsampling enabled (x_odd_inc = 3, y_odd_in c = 3). the frame rates assume a pixel rate of 64 mp/s (vt_pix_clk = 64 mhz) and th e minimum line blanking of 574 pixels/ minimum frame blanki ng of 85 lines. valid data signal options integration time the integration (exposure) time of the MT9M019 is controlled by the fine_integration_ time and coarse_integrat ion_time registers. the limits for the fine inte gration time are defined by: (eq 10) the limits for the coarse integration time are defined by: (eq 11) if coarse_integration_time>(frame_length_li nes-coarse_integration_time_max_margin) then the frame rate will be reduced. the actual integratio n time is given by: (eq 12) with default settings and a vt_pix_clk of 64 mhz, the maximum integration time that can be achieved without reducing the frame rate is given by: (eq 13) table 13: frame rates programmed image size resulting image size resulting frame rate subsampling disabled subsampling enabled subsampling disabled subsampling enabled 1280 x 1024 1280 x 1024 640 x 512 31.12 88.30 1024 x 768 1024 x 768 512 x 384 46.95 125.65 640 x 512 640 x 512 320 x 256 88.3 209.93 352 x 288 352 x 288 176 x 144 185.29 372.63 fine_integration_time_min < = fine_integration_time < = line_length_pck-fine_integration_time_max_margin () coarse_integration_time_min < = coarse_integration_time integration_time [sec] coarse_integration_time*line_length_pck ) "" fine_integration_time + () vt_pix_clk_freq_mhz 1 10 6 () ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------- = maximum integration time [sec] 0x4e4-1 () *0x8ec () +0x7ec () 64 mhz 1 10 6 () --------------------------------------------------------------------------- - 44.721 ms ==
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 34 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features setting an integration time that is greater than the frame time therefore increases the frame time beyond frame_length_lines to ma ke longer exposure times available. note that the frame length is now set by (coarse_integration_time - coarse_integration_time_max_margin) rather than the frame_length_lines . this should be taken into account for all other formulae us ed in this document. it is fundamental to the operation of an ers that it is not possible to set an integration time that is greater than the frame time. flash control the MT9M019 supports both xenon and led flash through the flash output signal. the timing of the flash signal with the default settings is shown in figure 18, 19, and 20. the flash and flash_count re gisters allow the timing of the flash to be changed. the flash can be programmed to fire only once, be delayed by a few frames when asserted, and (for xenon flash) the flas h duration can be programmed. enabling the led flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. th is can be avoided by forcing a restart (write reset_register[1] = 1) immediately after enabling the flash; the first bad frame will then be masked out as shown in figure 20. read-only bi t flash[14] is set during frames that are correctly integrated; the state of this bit is shown in figures 18, 19 and figure 20 on page 35. figure 18: xenon flash enabled figure 19: led flash enabled note: integration time = number of rows in a frame. frame valid flash strobe s tate of triggered bit (r0x3046-7[14]) bad fram e frame valid flash strobe s tate of triggered bit (r0x3046-7[14]) flash enabled bad frame good frame good frame flash disabled during this frame during this f rame
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 35 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features figure 20: led flash enabled following forced restart low power mode the sensor supports a low-power mode by programming a sequence of registers: set read mode register bit 9 (r0x3040?1[9]) = 1 set fine correction register (r0x3010?1) = 0x52 programming this sequence will change the min_line_pck. it is important that the line_length_pck formula in table 5 on page 14 is upheld at all times. line_length_pck <=((x_addr_end - x_addr_sta rt + 1)/xskip) + min_line_blanking_pck setting read _mode[9] bit will result in the following: ? double the value of pc_speed[2:0] internal ly. this means halving the internal pixel clock frequency. ? replace analog dac settings with low power settings. please be aware of the following fine_integration_time limits: fine_integration_time_min(r0x1008?9) = 0xf0 fine_integration_time_max_margin (r0x100a?b) = 0x7a the slower pixel clock provides more time for settling in the analog domain, thus, the low power dac values can be approximately half the full power dac values. enabling the low-power mode will not put the sensor in subsampling mode; this has to be programmed separately. low power is independent of the readout mode, and can also be enabled in full resolution mode. however, since the pixel clock speed is halved, the frame rates that can be ac hieved with low power mode are lower than in full power mode. only internal pixel clock speeds of 1, 2, and 4 are supported; therefore, low power mode combined with pc_speed[2:0] = 4 is an illegal combination. any limitations related to changing the intern al pixel clock speed will also apply to low power mode since it automatically changes the pixel clock speed. smia limiter registers therefore need to be reprogrammed by the host to match the new internal pixel clock frequency. flash enabled masked out good frame good frame flash disabled and a restart frame and a restart triggered triggered frame valid flash strobe s tate of triggered bit (r0x3046-7[14]) masked ou t frame
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 36 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features analog gain the MT9M019 provides two mechanisms for setting the analog gain. the first uses the smia gain model. the second uses the traditional aptina gain model. the following sections describe both models, the mapping between the models, and the operation of the per-color and global gain control. using per-color or global gain control the read-only analogue_gain_capa bility register returns a value of 1, indicating that the MT9M019 provides per-color gain control. however, the MT9M019 also provides the option of global gain control. per-color an d global gain control can be used interchange- ably. a write to a global gain register is alia sed as a write of the same data to the four associated color-dependent gain registers. a read from a global gain register is aliased to a read of the associated green1/greenr gain register. the read/write gain_mode register required by smia has no defined function in the smia specification. in the MT9M019 this regi ster has no side-effects on the operation of the gain; per-color and global gain control can be used interchangeably regardless of the state of the gain_mode register. smia gain model the smia gain model uses the following registers to set the analog gain: ? analogue_gain_code_global ? analogue_gain_code_greenr ? analogue_gain_code_red ? analogue_gain_code_blue ? analogue_gain_code_greenb the smia gain model requires a uniform step size between all gain settings. the analog gain is given by: (eq 14) aptina gain model the aptina gain model uses the following registers to set the analog gain: ? global_gain ?green1_gain ? red_gain ? blue_gain ?green2_gain this gain model maps directly to the control settings applied to the gain stages of the analog signal chain. this prov ide a 7-bit gain stage and a 2x gain stage. as a result, the step size varies depending upon whether the 2x gain stage is enabled. the analog gain is given by: (eq 15) gain analogue_gain_m0 analogue_gain_code analogue_gain_c1 -------------------- --------------------- --------------------- --------------------- ------------------- analogue_gain_code_ 8 ------------------ ------------------ ------------------ ---------------- - = = gain _gain[7] 1 + () _gain[6:0] 16 --------------- -------------- -------------- - =
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 37 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor features as a result of the 2x gain stage, many of the possible gain settings can be achieved in two different ways. for example, red_gain = 0x90 provides the same gain as red_gain = 0x20. the first example uses the 2x gain stage and the second example does not. in all cases, the preferred setting is the setting that enables the 2x gain stage, since this will result in lower noise. gain code mapping the aptina gain model maps directly to the underlying structure of the gain stages in the analog signal chain. when the smia gain model is used, gain codes are translated into equivalent settings in the aptina gain model. when the smia gain model is in use and values have been written to the analogue_gain_code_ registers, the as sociated value in the aptina gain model can be read from the associated _gain register. in cases where there is more than one possible mapping, the 2x gain stage is enabled, to provide the mapping with the lowest noise. when the aptina gain model is in use and values have been written to the gain_ registers, data read from th e associated analogue _gain_code_ register is unde- fined. the reason for this is that many of the gain codes available in the aptina gain model have no corresponding value in the smia gain model. the result of this is that the two gain models can be used interchangeably but, having written gains through one set of registers, those gains should be read back through the same set of registers.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 38 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path sensor core digital data path test patterns the MT9M019 supports a number of test patt erns to facilitate system debug. test patterns are enabled using test_pattern_mode (r0x0600?1). the test patterns are listed in table 14. test patterns 0?3 replace pixel data in the output image (the embedded data rows are still present). test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). for all of the test patterns, the MT9M019 regi sters must be set appropriately to control the frame rate and output timing. this includes: ?all clock divisors ? x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ?line_length_pck ?x_output_size ? y_output_size effect of data path processing on test patterns test patterns 1?3 are introduced early in the pi xel data path. as a result, they are affected by pixel processing that occurs wi thin the data path. this includes: ? noise cancellation ? black pedestal adjustment ? dark current compensation these effects can be eliminated by the following register settings: ? r0x3044?5[10] = 0 ? r0x30ca?b[0] = 1 ? r0x30cc?d = 0 ? r0x30ce?f = 0 ? r0x30d0?1 = 0 ? r0x30d2?3 = 0 ? r0x30c0?1[0] = 0 ? r0x30c2?3 = 0 ? r0x30c4?5 = 0 ? r0x30c6?7 = 0 table 14: test patterns test_pattern_mode description 0 normal operation: no test pattern 1 solid color 2 100% color bars 3 fade-to-gray color bars 4 pn9 link integrity pattern
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 39 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path ? r0x30c8?9 = 0 ? r0x301a?b[3] = 0 (enable writes to data pedestal) ? r0x301e?f = 0x0000 (set data pedestal to ?0?) ? r0x31e0[0] = 0 solid color test pattern in this mode, all pixel data is replaced by fixed bayer pattern test data. the intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenr, test_data_blue, test_data_greenb). 100 percent color bars test pattern in this test pattern, shown in figure 21, all pixe l data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). each bar is 160 pixels wide and occupies the full height of the output image. each color compo- nent of each bar is set to either ?0? (fully off ) or 0x3ff (fully on for 10-bit data). the pattern repeats after 8 * 160 = 1280 pixels. the image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_output_size. the color-bar pa ttern starts at the column identified by x_addr_start. the number of colors that ar e visible in the output is dependent upon x_addr_end - x_addr_start and the setting of x_output_size. the width of each color-bar is fixed at 160 pixels. the effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reversed. the black bar appears on the left side of the output image. any pattern repeat occu rs on the right side of the output image regardless of the setting of horizontal_mirror. the state of vertical_flip has no effect on this test pattern. the effect of subsampling and sc aling of this test pattern is undefined. figure 21: 100 percent color bars test pattern horizontal mirror = 0 horizontal mirror = 1
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 40 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path fade-to-gray color bars test pattern in this test pattern, shown in figure 22 on page 41, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). each bar is 160 pixels wide and occu pies 1,024 rows of the output image. each color bar fades vertically from full intensit y at the top of the image to 50 percent inten- sity (mid-gray) on the 1024th row. each color ba r is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps every 8 pixels for a given color. due to the bayer patte rn of the colors, this means that the level changes every 16 rows. the pattern repeats horizontally after 8 * 200 = 1600 pixels and vertically after 1,024 rows. using 10-bit data, the fade-to-gray pattern goes from 100 to 50 percent or from 0 to 50 percent for each color component, so only half of the 2 10 states of the 10-bit data are used. however, to get all of the gray levels, each state must be held for two rows, hence the vertical size of 2 10 / 2 * 2 = 1024. the image size is set by x_addr_start, x_ad dr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_ output_size. the color-bar pattern starts at the column identified by x_addr_start. the number of colors that are visible in the output is dependent upon x_addr_end - x_ad dr_start and the setting of x_output_size. the effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed. the black bar appears on the left side of the output image. any pattern repeat occurs on the right side of the output image regardless of the setting of horizontal_mirror. the effect of subsampling and sc aling of this test pattern is undefined.
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 41 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path figure 22: fade-to-gray color bars test pattern note: figures are for illustration purposes only. horizontal mirror = 0, vertical flip = 0 h orizontal mirror = 0, vertical flip = 1 horizontal mirror = 1, vertical flip = 0 horizontal mirror = 1, vertical flip = 1
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 42 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path pn9 link integrity pattern this test pattern provides a 512-bit pseudo-ran dom test sequence to test the integrity of the serial pixel data output stream. the polynomial x 9 + x 5 + 1 is used. the polynomial is initialized to 0x1ff at the start of each frame. when this test pattern is enabled: ? the embedded data rows are disabled an d the value of frame_format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present. ? the whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is fill ed with data from the pn9 sequence. test cursors the MT9M019 supports one horizontal and one vertical cursor, allowing a ?cross-hair? to be superimposed on the image, or on test patterns 1?3. the position and width of each cursor are programmable. only even cursor positions and even cursor widths are supported (this is a consequence of the internal architecture of the pixel array). each cursor can be inhibited by setting its width to ?0.? the programmed cursor position corresponds to an absolute row or column in the pixel array. for example, setting horizontal_cursor_ position to the same value as y_addr_start would result in a horizontal cursor being dr awn starting on the first row of the image. the cursors are opaque (they replace data fr om the imaged scene or test pattern). the color of each cursor is set by the values of the bayer components in the test_data_red, test_data_greenr, test_d ata_blue and test_data_ greenb registers. as a consequence, the cursors are the same color as test pattern 1 and are therefore invisible when test pattern 1 is selected. when vertical_cursor_position = 0x07ff, the vertical cursor operates in an automatic mode in which its position advances every fram e. in this mode the cursor starts at the column associated with x_addr_start = 0 and advances by a step-size of 8 columns each frame, until it reaches the column associat ed with x_addr_start = 2040, after which it wraps (256 steps). note that the active pixel array is smaller than this, so in the last 56 steps, the cursor will not be visible. the width and color of the cursor in this auto- matic mode are controlled in the usual way. the effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the smia specification. th e behavior of the MT9M019 is shown in figure 23 on page 43, where the test cursors are shown as translucent, for clarity. in prac- tice, they are opaque (they overlay the im aged scene). the manner in which the test cursors are affected by the value of imag e_orientation can be understood from the following implementation details: ? the test cursors are inserted early in the da ta path, so that they correlate to rows and to columns of the physical pixel array (rat her than to x and to y coordinates of the output image). ? the drawing of a cursor starts when the pixel array row or column address matches the value of the associated cursor_position re gister. as a result, the cursor start posi- tion remains fixed, relative to the rows an d columns of the pixel array, for all settings of image_orientation. ? the cursor generation continues until the appropriate cursor_width pixels have been drawn. the cursor width is generated from the start position and proceeds in the direction of pixel array readout. as a result , each cursor is reflected about an axis
pdf: 7723845879/source:2828556980 aptina reserves the right to change products or specifications without notice. mt9d019_ds - rev. f 5/10 en 43 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor sensor core digital data path corresponding to its start position when the appropriate bit is set in the image_orientation register. figure 23: test cursor behavior C image_orientation digital gain integer digital gains in the range 0?7 can be programmed. a digital gain of ?0? sets all pixel values to ?0? (the pixel data will simply represent the value applied by the pedestal block). pedestal this block adds value from the data_pedestal_ register (r0x301e?f[9:0] to the incoming pixel value. the data_pedestal_ register is read-only by default but can be made read/write by clearing the lock_reg bit in reset_register (r0x301a?b). the only way to disable the effect of the pedestal is to set it to ?0.? readout direction vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 1 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 1 readout direction readout direction r eadout d irection
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 44 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor mechanical specifications mechanical specifications figure 24 shows the die outline, including th e readout orientation, the optically-active area, and the offset of the optical center from the die center. figure 24: die outline 1 2 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 10 11 12 13 14 15 16 17 optical center from die center (280.00m, 0.00m) die center (0m, 0m) +y -y +x -x pad 1 (table 1) or center of die (table 2) pixel array first clear pixel (col. 88, row 40) last clear pixel (col. 1,375, row 1,071) die id and logo location
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 45 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor spectral characteristics spectral characteristics figure 25: quantum efficiency figure 26: cra vs. image height cra vs. image height plot image height cra (deg) (%) (mm) 000 5 0.090 2.18 10 0.180 4.32 15 0.270 6.41 20 0.361 8.48 25 0.451 10.49 30 0.541 12.45 35 0.631 14.33 40 0.721 16.11 45 0.811 17.77 50 0.902 19.29 55 0.992 20.64 60 1.082 21.82 65 1.172 22.80 70 1.262 23.58 75 1.352 24.16 80 1.442 24.55 85 1.533 24.77 90 1.623 24.84 95 1.713 24.82 100 1.803 24.75 0 5 10 15 20 25 30 35 40 45 50 350 450 550 650 750 850 950 1050 w avelengt h (nm) quantum efficiency (%) blue green (b) green (r) red 0 5 10 15 20 25 30 cra (deg) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 image height (%)
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 46 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications electrical specifications extclk the electrical characteristics of the extclk input are shown in table 15. the extclk input supports either an ac-coupled sine -wave input clock or a dc-coupled square- wave input clock. if extclk is ac-coupled to the MT9M019 and the clock is stopped, the extclk input to the MT9M019 must be driven to ground or to v dd io. failure to do this will result in excessive current consumption within the extclk input receiver. table 15: electrical characteristics (extclk) f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit f extclkin1 input clock frequency pll enabled 6 16 27 mhz t extclkin1 input clock period pll enabled 166 62.5 37 ns t r input clock rise time 0.03 C 1 v/ns t f input clock fall time 0.03 C 1 v/ns v in _ ac input clock minimum voltage swing (ac coupled) 0.5 C C v (p-p) v in _ dc input clock maximum voltage (dc coupled) v dd Cv dd + 0.1 v f clkmax(ac) input clock signalling frequency (low amplitude) v in = v in _ ac (min) C C 27 mhz f clkmax(dc) input clock signalling frequency (full amplitude) v in = v dd CC clock duty cycle 45 50 55 % t jitter input clock jitter C C 300 ps t cp extclk to pixclk propagation delay CCns pll enabled C 5 C t lock pll vco lock time pll enabled C 0.5 1 ms c in input pad capacitance C 2.5 C pf i ih input high leakage current C 2.5 10 a i il input low leakage current C 2.5 C10 a
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 47 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications two-wire serial register interface the electrical characteristics of the two- wire serial register interface (sclk, s data ) are shown in table 16. the sclk and s data signals feature fail-s afe input protection, schmitt trigger input, and suppression of in put pulses of less than 50ns duration. notes: 1. the two-wire serial registers interface does not drive output to high; the high signal state is achieved through the pull-up resistors. serial pixel data interface the electrical characteristics of the serial pixel data interface (clkp, clkn, datap, datan) are shown in table 17. to operate the serial pixel data interface with in the electrical limits of the ccp2 specifi- cation, vddccp (v dd io) is restricted to operate in the range 1.7?1.9v. table 16: two-wire serial register interface electrical characteristics f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit note v ih input high voltage 0.7 x v dd Cv dd + 0.5 v v il input low voltage C0.5 C 0.3v x v dd v i in input leakage current no pull-up resistor; v in = v dd or d gnd C10 C a v oh output high voltage at specified i oh 8ma, v dd = 1.8v C v dd Cv1 v ol output low voltage at specified i ol 8ma, v dd = 1.8v 0.16 C 0.35 v 1 i oh output high current at specified v oh max, v dd = 1.8v 8.9 C 22.3 ma i ol output low current at specified v ol 0.1v 2.6 C 5.1 ma i ol output low current at specified v ol 0.4v 8.9 C 18.5 ma i o z tri-state output leakage current CC 1 a c in input pad capacitance C C 6 pf c load load capacitance C C n/a pf table 17: electrical characteristics (serial pixel data interface) f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit operating frequency 1 C 320 mhz v cmf fixed common mode voltage 0.8 0.9 1 v vod differential voltage swing 100 155 200 mv drive current range 0.83 1.5 2 ma drive current variation C C 15 % output impedance 40 58 140 output impedance mismatch C4 10% clock duty cycle @ 416 mhz 45 50 55 % vod rise time (20C80%) 300 330 400 ps
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 48 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications control interface the electrical characteristics of the control interface (reset_n, s addr [through gpi], test, gpi0, gpi1) are shown in table 18. power-on reset vod fall time (20C80%) 280 300 470 ps differential skew C 300 500 ps channel-to-channel slew C C 200 ps maximum data rate data/strobe mode data/clock mode CC 640 208 mb/s power supply rejection ratio (psrr) 0C100 mhz 30 C C db power supply rejection ratio (psrr) 100C1,000 mhz 10 C C db table 18: ac electrical characteristics (control interface) f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit v ih input high voltage 0.7 x v dd Cv dd + 0.5 v v il input low voltage C0.3 C 0.3 x v dd v i in input leakage current no pull-up resistor; v in = v dd or d gnd C<10 C a c in input pad capacitance C 6.5 C pf table 19: power-on reset characteristics symbol parameter condition min typ max unit t 1v dd rising, crossing v trig _ rising ; internal reset being released 71015 s t 2v dd falling, crossing v trig _ falling ; internal reset active C0.51 s t 3 minimum v dd spike width below v trig _ falling ; considered to be a reset when por cell output is high C0.5C s t 4 minimum v dd spike width below v trig _f alling ; considered to be a reset when por cell output is low C1C s table 17: electrical characteristics (serial pixel data interface) (continued) f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 49 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications figure 27: internal power-on reset operating voltages v aa and vaapix must be at the same potent ial for correct operation of the MT9M019. t 5 minimum v dd spike width above v trig _ rising ; considered to be a stable supply when por cell output is low while the por cell output is low, all v dd spikes above v trig _ rising less than t 5 must be ignored C50Cns v trig _ rising v dd rising trigger voltage 1.12 C 1.55 v v trig _ falling v dd falling trigger voltage 1.0 C 1.45 v table 20: dc electrical definitions and characteristics f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd ccp (v dd io) i/o digital voltage serial pixel (ccp2) data interface 1.7 1.8 1.9 v v aa analog voltage 2.4 2.8 3.1 v vaapix pixel supply voltage 2.4 2.8 3.1 v v dd pll pll supply voltage 2.4 2.8 3.1 v i dd 1 digital operating current streaming, full resolution C 18 30 ma i dd 2 i/o digital operating current streaming, full resolution C 10 12 ma i aa analog operating current streaming, full resolution C 42 50 ma iaapix pixel supply current streaming, full resolution C 1.4 1.9 ma i ddpll pll supply current streaming, full resolution C 5 7 ma hard standby (clock off) analog 0 C 10 a digital 10C50 a hard standby (clock on (6 mhz)) analog 10 C 50 a digital 160 C 250 a table 19: power-on reset characteristics (continued) symbol parameter condition min typ max unit digital power supply v dd por cell output por cell output t 1 burst < t 4 v trig _ rising v trig _ falling burst > t 2 burst < t 5 burst > t 5 burst < t 2 t 3 t 1
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 50 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications soft standby (clock off) analog (vco power down) 0 C 20 a digital (vco power down) 10 C 50 a soft standby (clock on (6 mhz)) analog (vco power down) 10 C 50 a digital (vco power down) 160 C 250 a table 21: smia characterization data table default power supply voltage: vdig = 1.8 +/- 0.1v, vana = 2.8 +/- 0.1v parameter at 23+/- 2c ~ 40c, at 40c: except resolution and color accuracy testing sensor dependency parameters parameters lower limit typical upper limit units (smia) sensitivity 0.07 1/(cdm-2*sec) photo response non-uniformity (prnu) 0.8 % module response non-linearity integral non-linearity: 50% 0.00024 codes/fsd differential non-linearity: 50% 0.00458 ratio snr 10 cd/m 2 36.60 db 50 cd/m 2 36.61 db 100 cd/m 2 36.05 db 450 cd/m 2 36.31 db maximum illumination (minimum integration time = 28?sec) 4.76e+05 cd/m 2 minimum illumination (maximum integration time = 266ms) 2.64e-02 cd/m 2 dynamic range (msr settings for smia test : ???) 66.05 db vertical fpn level 3.5e-04 codes/fsd max 6.9e-04 codes/fsd horizontal fpn level 8.1e-05 codes/fsd max 1.8e-04 codes/fsd temporal noise -61.26285412 db column noise level -86.04232908 db max -84.68667414 db row noise level -68.46697445 db max -66.74710259 db frame-to-frame flicker 8.43e-04 codes/pedestal dark signal 3.96e-04 (sec)-1 dark signal non-uniformity (dsnu) 8.99e-04 (sec)-1 power supply rejection ratio (psrr): value * : in case of smia test method which fixed amplitude noise psrr at 50hz ~10 khz * 69.91 db psrr at ~1 mhz * 42.16 db psrr at ~10 mhz * 64.28 db image lag as wafer level test data <0.05 % table 20: dc electrical definitions and characteristics (continued) f extclk = 16 mhz; v dd = 1.8v; v dd ccp (v dd io) = 1.8v; v aa = 2.8v; vaapix = 2.8v; v dd pll = 2.8v; output load = 68.5pf; ambient temperature; 0 lux on sensor symbol parameter conditions min typ max unit
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 51 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications notes: 1. all the tests were performed using a rev 3 sensor at gain = 1 and at room temperature except for dsnu, which was performed at gain = 15.875 and at 50c. smia color accuracy mean 3.53 e*ab standard deviation 2.16 e*ab maximum 10.09 e*ab table 22: electrical characteristics (flash) f extclkin = 16 mhz; v dd = 1.8v; v dd io = 1.8v; vaa = 2.8v; vaapix = 2.8v; vddpll = 2.8v; output load = 68.5; ambient temperature symbol parameter conditions min typ max unit v oh output high voltage at specified i oh 8ma v dd io C0.5 C C v v ol output low voltage at specified i ol 8ma C 0.4 v i oh output high current at specified v oh min, v dd io = 1.8v 2.7 C 6.4 ma i oh output high current at specified v oh max, v dd io = 1.8v 8.9 C 22.3 ma i ol output low current at specified v ol 0.1v 2.6 C 5.1 ma i ol output low current at specified v ol 0.4v 8.9 C 18.5 ma i oz tri-state output leakage current C C 1 a ouput pin slew default, c load = 30pf C 0.3818 C v/ns table 21: smia characterization data table default power supply voltage: vdig = 1.8 +/- 0.1v, vana = 2.8 +/- 0.1v parameter at 23+/- 2c ~ 40c, at 40c: except resolution and color accuracy testing sensor dependency parameters parameters lower limit typical upper limit units (smia)
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 52 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor electrical specifications absolute maximum ratings caution stresses greater than those listed may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. smia specification reference the part itself and this documentation is based on the following smia reference docu- ments: ? functional specification: ? smia 1.0 part 1: functional specification (version 1.0 dated 30-june-2004); smia 1.0 part 1: functional specification ecr0001 (version 1.0 dated 11-feb-2005) ? electrical specification: ? smia 1.0 part 2: ccp2 specification (version 1.0 dated 30-june-2004); smia 1.0 part 2: ccp2 specification ecr0002 (version 1.0 dated 11-feb-2005) table 23: absolute maximum values symbol parameter conditions min typ max unit v dd _ max core digital voltage C0.3 C 1.9 v v dd _ max i/o digital voltage C0.3 C 1.9 v v aa _ max analog voltage C0.3 C 3.1 v v aapix _ max pixel supply voltage C0.3 C 3.1 v v ddpll _ max pll supply voltage C0.3 C 3.1 v v ih _ max input high voltage 0.7 x v dd Cv dd + 0.5 v v il _ max input low voltage C0.3 C 0.3 x v dd v i dd _ max digital operating current worst case current C C 80 ma i dd _ max i/o digital operating current worst case current C C 15 ma i aa _ max analog operating current worst case current C C 70 ma i aapix _ max pixel supply current worst case current C C 3 ma i ddpll _ max pll supply current worst case current C C 8 ma t op operating temperature measure at junction C30 C 70 c t stg storage temperature C40 C 125 c
pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 53 ?2006 aptina imaging corporation. all rights reserved. MT9M019: 1/5-inch 1.3mp cmos digital image sensor revision history revision history rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/26/10 updated to non-confidential rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/10 updated to aptina template rev. d, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/30/2007 ? updated table 23, ?absolute maximum values,? on page 52 ? updated data sheet to production status rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/26/2007 ? update table 1, ?key performance parameters,? on page 1 ? remove figure 27: ?internal power-on reset,? on page 49 ? update table 20, ?dc electrical defini tions and characteristics,? on page 49 ? add table 21, ?smia characterization data table,? on page 50 ? add table 22, ?electrical characteristics (flash),? on page 51 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/06 ? update table 1, ?key performance parameters,? on page 1 ? update figure 2: ?typical configuration: serial pixel data interface,? on page 7 ? update "effect of ccp2 class on legal range of output sizes/frame rate" on page 17 ? update figure 11: ?MT9M019 system states,? on page 21 ? update "power-on reset sequence" on page 22 ? table 6, ?pll in system states,? on page 21 ? update "power-on reset sequence" on page 22 ? update "general purpose inputs" on page 23 ? update figure 12: ?MT9M019 smia profile 1, 2 clocking structure,? on page 24 ? add "programming example" on page 28 ? add table 11, ?default settings,? on page 28 ? update table 12, ?row address sequencing,? on page 32 ? update table 13, ?frame rates,? on page 33 ? update "frame rates at common image sizes" on page 33 ? update "low power mode" on page 35 ? update "aptina gain model" on page 36 ? update table 13, ?frame rates,? on page 33 ? update "low power mode" on page 35 ? update table 14, ?test patterns,? on page 38 ? update "effect of data path proce ssing on test patterns" on page 38 ? update "fade-to-gray color bars test pattern" on page 40 ? update "100 percent color bars test pattern" on page 39 ? update "test cursors" on page 42 ? update "pedestal" on page 43 ? remove embedded data format and control section ? remove table 23, ?embedded data? ? update figure 24: ?die outline,? on page 44 ? update table 25, ?quantum efficiency,? on page 45 ? add figure 26: ?cra vs. image height,? on page 45
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9M019: 1/5-inch 1.3mp cmos digital image sensor revision history pdf: 7723845879/source: 2828556980 aptina reserves the right to change products or specifications without notice. MT9M019_ds - rev. f 5/10 en 54 ?2006 aptina imaging corporation all rights reserved. ? update figure 27: ?internal power-on reset,? on page 49 ? update table 15, ?electrical char acteristics (extclk),? on page 46 ? update table 17, ?electrical characteristics (serial pixel data interface),? on page 47 ? update table 18, ?ac electrical characte ristics (control interface),? on page 48 ? update table 20, ?dc electrical defini tions and characteristics,? on page 49 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/06 ?initial release

▲Up To Search▲

Price & Availability of MT9M019

	To Download MT9M019 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .